A complete monolithic sample/hold amplifier

A monolithic sample/hold amplifier is described which includes the holding capacitor on the chip. System design considerations and tradeoffs are discussed, as well as the circuit design details. High performance is achieved by the use of a process which produces bipolar transistors and p-channel silicon-gate FET´s (SIGFET´s) on the same chip. Performance characteristics obtained include an acquisition time of 10 /spl mu/s (20-V step), an aperture delay time of 80 ns, and a droop rate of 30 mV/s.