DocumentCode
880982
Title
A monolithic 8-bit D/A converter with a new scheme for error compensation
Author
Shoji, Mamoru ; Saari, V.R.
Volume
10
Issue
6
fYear
1975
Firstpage
499
Lastpage
501
Abstract
Discusses a modification of a monolithic bipolar 8-bit D/A converter (DAC) circuit based on the R-2R ladder method. It does not require transistor emitter size scaling. Voltages proportional to absolute temperature are introduced between the bases of the current generator transistors to compensate for the differences in their emitter-base voltages and thus maintain precision in the current division of the R-2R ladder. The compensation obtained by this method is adequate for 9- and 10-bit monolithic DAC´s operating in a temperature range from -40/spl deg/C to 125/spl deg/C.
Keywords
Bipolar transistors; Convertors; Digital-analogue conversion; Error compensation; Monolithic integrated circuits; bipolar transistors; convertors; digital-analogue conversion; error compensation; monolithic integrated circuits; Channel bank filters; Circuits; Computational modeling; Computer simulation; Error compensation; Parasitic capacitance; Signal to noise ratio; Switches; Telephony; Voltage;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1975.1050647
Filename
1050647
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