Title :
A monolithic 8 pJ/2 GHz logic family
Author :
Sudo, Tsuneta ; Kamoto, Tsutomu ; Mukai, Hisakazu ; Sasaki, Hajime ; Morino, Akihiko ; Shiba, Hiroshi
Abstract :
Discusses a monolithic logic family developed for high-speed communication systems usage. The logic family affords 8 pJ speed-power product, 2 GHz toggle frequency and 400 ps/gate propagation delay time in 50/spl Omega/ transmission systems. The primary factor for realizing the high-speed, low-power operation is new circuit configuration: modified nonthreshold logic (NTL). Transistors in this circuit are made to operate almost in the active region which increases switching speed. In addition, a novel master slave flip-flop configuration is designed to operate with propagation delay nearly equal to that of gate. The device was fabricated by using junction isolated transistors with an emitter stripe width of 2 /spl mu/ and cutoff frequency of 4 GHz. This paper describes the circuit design and performance of developed logic family.
Keywords :
Bipolar transistors; Digital communication systems; Digital integrated circuits; Flip-flops; Logic circuits; Monolithic integrated circuits; bipolar transistors; digital communication systems; digital integrated circuits; flip-flops; logic circuits; monolithic integrated circuits; Circuit noise; Costs; Electron devices; Logic circuits; Logic devices; Operational amplifiers; Propagation delay; Solid modeling; Solid state circuits; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1975.1050653
