A 12 Bit 1.6 GS/s BiCMOS 2×2 Hierarchical Time-Interleaved Pipeline ADC

This paper describes a 12 bit 1.6 GS/s pipeline ADC realized in a 0.18 μm complementary BiCMOS SiGe process. The ADC consists of a four-way time-interleaved hierarchical structure and a master-slave T&H to improve the dynamic performance of the individual sub-ADCs and to reduce both the converter error rate and the complexity of the required interleaving background calibration algorithms. It achieves an SFDR of 79 dBc and 66 dBc at low and high frequency inputs, respectively and an error rate of less than 10^-9, and has a power consumption of 1.15 W for the core ADC.