Characteristics of a Novel Poly-Si P-Channel Junctionless Thin-Film Transistor With Hybrid P/N-Substrate

Author

Ya-Chi Cheng ; Hung-Bin Chen ; Jun-Ji Su ; Chi-Shen Shao ; Thirunavukkarasu, Vasanthan ; Chun-Yen Chang ; Yung-Chun Wu

Author_Institution

Dept. of Eng. & Syst. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan

Volume

36

Issue

2

fYear

2015

fDate

Feb. 2015

Firstpage

159

Lastpage

161

Abstract

This letter for the first time proposes a hybrid P/N substrate as a poly-Si p-channel for junctionless thin-film transistor (JL-TFT) with nanowires and omega-gate structures. The hybrid P/N JL-TFT exhibits a high ION/IOFF current ratio (>10⁷), a steep subthreshold swing of 64 mV/dec, and a low drain-induced barrier lowering value of 3 mV/V by reducing the effective channel thickness that is caused by the channel/substrate junction. In addition, the series resistance for novel P/N JL-TFT with channel thickness (T_ch) of 24 nm is 50 times smaller than conventional JL-TFT with T_ch = 12 nm. This hybrid P/N structure can break through the strict limitation of JL-TFT channel thickness.

Keywords

elemental semiconductors; nanowires; silicon; thin film transistors; JL-TFT channel thickness; Si; hybrid P-N substrate; nanowires; omega-gate structures; poly-Si p-channel junctionless thin-film transistor; size 24 nm; substrate junction; Doping; Junctions; Logic gates; Nanowires; Performance evaluation; Substrates; Thin film transistors; Junctionless (JL); nanowires (NWs); omega-gate; thin-film transistor (TFT);

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2014.2379673

Filename

6982215