Design and characterization of analog VLSI neural network modules

Author

Gowda, Sudhir M. ; Sheu, Bing J. ; Choi, Joongho ; Hwang, Chang-Gyu ; Cable, James S.

Author_Institution

Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA

Volume

28

Issue

3

fYear

1993

fDate

3/1/1993 12:00:00 AM

Firstpage

301

Lastpage

313

Abstract

A systematic method for testing large arrays of analog, digital, or mixed-signal circuit components that constitute VLSI neural networks is described. This detailed testing procedure consists of a parametric test and a behavioral test. Characteristics of the input neuron, synapse, and output neuron circuits are used to distinguish between faulty and useful chips. Stochastic analysis of the parametric test results can be used to predict chip yield information. Several measurement results from two analog neural network processor designs that are fabricated in 2 μm double-polysilicon CMOS technologies are presented to demonstrate the testing procedure

Keywords

CMOS integrated circuits; VLSI; analogue processing circuits; neural nets; 2 micron; VLSI neural networks; analog VLSI neural network modules; analog neural network processor designs; behavioral test; characterization; chip yield prediction; double-polysilicon CMOS technologies; input neuron; mixed-signal circuit components; neural network design; output neuron circuits; parametric test; parametric test results; stochastic analysis; synapse; systematic method; testing procedure; CMOS technology; Circuit faults; Circuit testing; Information analysis; Neural networks; Neurons; Semiconductor device measurement; Stochastic processes; System testing; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.209997

Filename

209997