High-speed static programmable logic array in LOCMOS

Author

May, Peter ; Schiereck, Frans C.

Volume

11

Issue

3

fYear

1976

fDate

6/1/1976 12:00:00 AM

Firstpage

365

Lastpage

369

Abstract

A large static programmable logic array (PLA) with 20 inputs, 94 product terms, and 24 outputs, designed and realized in LOCMOS, the complementary MOS technology with isolation by local oxidation of silicon. Layout and physical parameters of this technology resulted in a simple, dense, and low-capacity design. The dc and transient features of different realization possibilities have been simulated. Design automation tools have been developed to ensure error-free personalization of the PLA. A density of 160 gates per mm/SUP 2/ has been achieved. Samples show average propagation delays of 100 ns, while dissipation is typically 120 mW.

Keywords

Digital integrated circuits; Field effect transistors; Integrated circuit production; Large scale integration; Logic circuits; Monolithic integrated circuits; digital integrated circuits; field effect transistors; integrated circuit production; large scale integration; logic circuits; monolithic integrated circuits; CMOS logic circuits; CMOS technology; Delay; Design automation; Isolation technology; Large scale integration; Logic design; Oxidation; Programmable logic arrays; Silicon;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1976.1050737

Filename

1050737