Study of BiCMOS logic gate configurations for improved low-voltage performance

Author

Tsui, Paul G Y ; Pappert, Bernie ; Sun, Shih Wei ; Yeargain, John R.

Author_Institution

Motorola Inc., Austin, TX, USA

Volume

28

Issue

3

fYear

1993

fDate

3/1/1993 12:00:00 AM

Firstpage

371

Lastpage

374

Abstract

A simple BiCMOS configuration employing the source-well tie PMOS/n-p-n pull-down combination is proposed for low-voltage, high-performance operations. The improved BiCMOS gate delay time over that of the NMOS/n-p-n (conventional) BiCMOS gate is confirmed by means of inverter simulations and measured ring oscillator data. The source-well tie PMOS/n-p-n BiCMOS gate outperforms its conventional BiCMOS counterpart in the low-voltage supply range, at both high and low temperatures. A critical speed path from the 68030 internal circuit is used as a benchmark for the proposed BiCMOS design technique. The measured propagation delay of the BiCMOS speed path is faster than its CMOS counterpart down to 2.3 V supply voltage at -10°C and sub-2 V at 110°C

Keywords

BiCMOS integrated circuits; delays; integrated logic circuits; logic gates; 2 V; 68030 internal circuit; BiCMOS logic gate; inverter simulations; low-voltage performance; n-p-n pull-down; propagation delay; source-well tie PMOS; temperature effects; BiCMOS integrated circuits; Circuit simulation; Delay effects; Inverters; Logic gates; MOS devices; Ring oscillators; Temperature distribution; Time measurement; Velocity measurement;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.210005

Filename

210005