Title :
A BiCMOS dynamic carry lookahead adder circuit for VLSI implementation of high-speed arithmetic unit
Author :
Kuo, J.B. ; Liao, H.J. ; Chen, H.P.
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fDate :
3/1/1993 12:00:00 AM
Abstract :
A BiCMOS dynamic carry lookahead circuit that is free from race problems is presented. A 16 b full-adder test circuit, which has been designed based on a 2 μm BiCMOS technology, shows a more than five times improvement in speed as compared to the CMOS Manchester carry lookahead (MCLA) circuit. The speed advantage of the BiCMOS dynamic carry lookahead circuit is even greater in a 32- or 64-b adder
Keywords :
BiCMOS integrated circuits; VLSI; adders; carry logic; digital arithmetic; integrated logic circuits; 2 micron; BiCMOS; VLSI implementation; adder circuit; dynamic carry lookahead circuit; high-speed arithmetic unit; race-free circuit; Adders; Arithmetic; BiCMOS integrated circuits; Circuit testing; Large-scale systems; Logic gates; Propagation delay; Signal generators; Signal processing; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
