Optimum load device for DMOS integrated circuits

Depletion-mode load devices can be integrated with DMOS transistors without any extra diffusions or implantation processing steps by judicious choice of the substrate crystal orientation and resistivity. For low voltage operation, <1,1,1> crystal orientation should be used. The <1,1,1> crystal orientation also yields a higher transconductance for the DMOS transistor than the <1,0,0> orientation. The geometry of the load device and the DMOS transistor can be made ratioless to conserve area. Self-aligned gates, hitherto considered incompatible with DMOS transistors, have been incorporated in the structure. The experimental DMOS invertors, using a conservative design, have achieved 4-ns propagation delay, 1.3-V operation and 2-pJ propagation delay-power dissipation product.