• DocumentCode
    882497
  • Title

    Two 4K static 5-V RAM´s

  • Author

    Schlageter, Jeffrey M. ; Jayakumar, Nagab ; Kroeger, Joseph H. ; Sarkissian, Vahe

  • Volume
    11
  • Issue
    5
  • fYear
    1976
  • fDate
    10/1/1976 12:00:00 AM
  • Firstpage
    602
  • Lastpage
    609
  • Abstract
    This paper describes two 4096-bit, static, TTL compatible, 5 V only, MOS RAM´s with worst case access times down to 200 ns and worst case power dissipations down to 370 mW. One is organized as 1K×4 and the other as 4K×1. Both devices are obtained from the same 192- by 197-mil die by a metal mask option and both are assembled in 22-pin dual-in-line packages. A novel memory status output signal is provided to allow the system designer to utilize actual memory performance rather than worst case data sheet specifications. This allows improved system benchmarks in addition to simplified timing.
  • Keywords
    Digital integrated circuits; Monolithic integrated circuits; Random-access storage; Semiconductor storage devices; digital integrated circuits; monolithic integrated circuits; random-access storage; semiconductor storage devices; Buffer storage; Clocks; Decoding; Pins; Power dissipation; Pulsed power supplies; Random access memory; Read-write memory; Timing; Voltage;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.1976.1050787
  • Filename
    1050787
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=882497