Yield enhancement with optimal area allocation for ratio-critical analog circuits

Parametric yield models for widely used area allocation schemes in ratio-critical analog circuits are developed. It is shown that some of the most widely used schemes are suboptimal and that significant improvements in parametric yield can be achieved with less intuitive area allocation approaches. Simulations results are presented which show quantitatively what improvements in yield can be achieved with improved area allocation strategies for resistive feedback amplifiers and R-2R ladders