Second generation I/sup 2/L/MTL: a 20 ns process/structure

Author

Herman, John M., III ; Evans, Stephan A. ; Sloan, Ben J., Jr.

Volume

12

Issue

2

fYear

1977

fDate

4/1/1977 12:00:00 AM

Firstpage

93

Lastpage

101

Abstract

A high performance, second generation I/SUP 2/L/MTL gate for digital LSI applications with TTL compatibility has successfully been designed, characterized, and demonstrated fully functional over a wide current range and the military temperature range of -55 to 125/spl deg/C. Performance is measured using an in-line five-collector gate having one end injector. The gate performed with the following characteristics at 100 /spl mu/A injector current: /spl beta//SUB U//SUP eff//spl ges/4 for all collectors at 25/spl deg/C and /spl ges/2.5 at -55/spl deg/C, /spl alpha//SUB rec///spl alpha//SUB F//spl cong/0.58 and /spl tau/~/SUB d/=18-20 ns from -55 to 125/spl deg/C, and a speed-power product of 1.4 pJ at 25/spl deg/C. At low injector currents, a constant speed-power product of 0.36 pJ at 25/spl deg/ was obtained.

Keywords

Bipolar integrated circuits; Integrated logic circuits; Large scale integration; bipolar integrated circuits; integrated logic circuits; large scale integration; Character generation; Circuits; Geometry; Isolation technology; Large scale integration; Measurement standards; P-n junctions; Propagation delay; Temperature distribution; Terminology;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1977.1050854

Filename

1050854