• DocumentCode
    883377
  • Title

    Modeling device and layout effects of performance driven I/sup 2/L

  • Author

    Gaffney, Donald P. ; Bhattacharyya, A.

  • Volume
    12
  • Issue
    2
  • fYear
    1977
  • fDate
    4/1/1977 12:00:00 AM
  • Firstpage
    155
  • Lastpage
    162
  • Abstract
    The performance of I/SUP 2/L gates at high injector current levels has been shown to be dependent on minority carrier charge storage and fan-out. These models, however, do not include the effects of extrinsic base resistance, parasitic diode shunting, and lateral p-n-p high level injection on the speed-power product curve. This paper considers these three factors with the aid of a device model, circuit simulations, and test data from logic race structures.
  • Keywords
    Bipolar integrated circuits; Integrated logic circuits; Semiconductor device models; bipolar integrated circuits; integrated logic circuits; semiconductor device models; Circuit simulation; Circuit testing; Delay effects; Diodes; Doping; Inverters; Logic testing; Metallization; Propagation delay; Upper bound;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.1977.1050865
  • Filename
    1050865
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=883377