A 2.7 GHz to 7 GHz Fractional-N LC-PLL Utilizing Multi-Metal Layer SoC Technology in 28 nm CMOS

Author

Chang-Hyeon Lee ; Kabalican, Lindel ; Yan Ge ; Kwantono, Hendra ; Unruh, Greg ; Chambers, Mark ; Fujimori, Ichiro

Author_Institution

Broadcom Corp., Irvine, CA, USA

Volume

50

Issue

4

fYear

2015

fDate

Apr-15

Firstpage

856

Lastpage

866

Abstract

A fractional-N LC-PLL in 28 nm CMOS that uses vertical layout integration techniques to achieve area reduction without performance penalties is proposed. The design utilizes multi-metal layers to vertically integrate dual interposed inductors on top of the active PLL circuit elements, resulting in an area of 0.07 mm². The PLL covers a wide-frequency range from 2.7 GHz to 7 GHz, consuming a total power of 14 mW. At 7 GHz, the RMS jitter is 0.56 ps in integer mode and 1.1 ps in fractional mode.

Keywords

CMOS analogue integrated circuits; UHF integrated circuits; inductors; integrated circuit design; microwave integrated circuits; phase locked loops; system-on-chip; CMOS technology; active PLL circuit element; dual interposed inductor; fractional-N LC-PLL; frequency 2.7 GHz to 7 GHz; multimetal layer SoC technology; power 14 mW; size 28 nm; time 0.56 ps; time 1.1 ps; vertical layout integration technique; Inductors; Metals; Noise; Phase locked loops; Substrates; Switches; Voltage-controlled oscillators; LC-PLL; active loop filter; capacitor multiplier; fractional-N synthesizers; patterned ground shield; spiral inductor;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2014.2371136

Filename

6982234