• DocumentCode
    883546
  • Title

    High-Speed Adders and Comparators Using Transistors and Tunnel Dioes

  • Author

    Amodei, J.J.

  • Author_Institution
    RCA David Sarnoff Research Center Princeton, N. J., and La Salle College, Philadelphia, Pa.
  • Issue
    5
  • fYear
    1964
  • Firstpage
    563
  • Lastpage
    575
  • Abstract
    Comparators and adders are among the circuits that can take best advantage of the combined properties of transistors and tunnel diodes. The paper describes a transistor-tunnel diode complementary output pair module that is used as a basis for several configurations of comparators, half adder and full adder circuits. The comparators and half adders are discussed qualitatively. A detailed design and tolerance analysis of the full adder circuit is presented and the design equations that will optimize the tolerance requirements are derived. A switching analysis of the carry portion of the full adder circuit is carried out. The results illustrate that stray elements rather than intrinsic device performance are the dominant factors contributing to carry delay in a conventionally wired system. The paper also describes the results of the tests made on an eight-bit adder system which was constructed with conventionally encapsulated devices and standard wiring. The average carry delay per stage in this system was ¿ nsec. The time required to obtain the correct final sum output was 3 to 5 nsec after arrival of the carry. Tests with specially encapsulated high-speed transistors and low-capacity gallium arsenide tunnel diodes showed 0.2-nsec carry delay and 2-nsec sum delay.
  • Keywords
    Adders; Circuit testing; Delay; Design optimization; Diodes; Equations; Switching circuits; System testing; Tolerance analysis; Wiring;
  • fLanguage
    English
  • Journal_Title
    Electronic Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0367-7508
  • Type

    jour

  • DOI
    10.1109/PGEC.1964.263727
  • Filename
    4038249