Title :
From wafer-level gate-oxide reliability towards ESD failures in advanced CMOS technologies
Author :
Kerber, A. ; Röhner, M. ; Wallace, C. ; O´Riain, L. ; Kerber, M.
Author_Institution :
Corp. Reliability Methodology Dept., Munich, Germany
fDate :
4/1/2006 12:00:00 AM
Abstract :
The impact of a short-term electrical overstress on dielectric reliability is thoroughly investigated using a dedicated experimental equipment for measurement times in the millisecond and microsecond range. Based on significant statistics, it is confirmed that the dielectric stress-induced damage is cumulative in nature. In addition, the voltage acceleration is shown to follow the power-law model towards the time range of electrostatic discharge and furthermore the breakdown statistics remain unchanged. These results justify the assessment of a short-term electrical overstress in advanced CMOS technologies by using a conventional reliability prediction methodology.
Keywords :
CMOS integrated circuits; dielectric materials; electrostatic discharge; integrated circuit reliability; ESD failure; advanced CMOS technology; dielectric reliability; power law model; voltage acceleration; wafer level gate oxide reliability; Acceleration; Breakdown voltage; CMOS technology; Dielectric measurements; Electric breakdown; Electrostatic discharge; Probability; Statistics; Stress; Testing; Breakdown statistics; dielectric reliability; electrostatic discharge (ESD); voltage acceleration;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2006.870517
