Title :
Dual depletion CMOS (D/sup 2/CMOS) static memory cell
Author :
Takagi, Hiromitsu ; Kano, Gota
Abstract :
A new type of static memory cell-dual depletion CMOS (D/SUP 2/MOS)-has been designed and fabricated using SOS wafers by the conventional CMOS/SOS technology. In contrast to the conventional CMOS static memory cell, which comprises six transistors, the new cell consists merely of four transistors and one data-line so that the cell area can be significantly reduced.
Keywords :
Field effect integrated circuits; Integrated memory circuits; field effect integrated circuits; integrated memory circuits; CMOS memory circuits; CMOS technology; Epitaxial layers; Fabrication; MOSFETs; Oxidation; Read-write memory; Solids; Threshold voltage; Writing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1977.1050924
