DocumentCode
884303
Title
Techniques for reducing the peak power of a switching transistor with p-i-n diode load
Author
Georgopoulos, Chris J.
Volume
12
Issue
5
fYear
1977
fDate
10/1/1977 12:00:00 AM
Firstpage
537
Lastpage
540
Abstract
Describes techniques for reducing the peak power of switching transistor that reverse biases a p-i-n diode load. Particular emphasis is placed on a parallel combination of a Zener diode and an inductor and it is shown that, for an experimental p-i-n driver, the peak power is reduced from 252 to 90 W.
Keywords
Bipolar transistors; Semiconductor diodes; Semiconductor switches; bipolar transistors; semiconductor diodes; semiconductor switches; Clamps; Impedance; Inductors; P-i-n diodes; Resistors; Stress; Switching circuits; Virtual manufacturing; Virtual reality; Voltage;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1977.1050951
Filename
1050951
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