DocumentCode
884402
Title
Reed-Muller universal logic module networks
Author
Xu, L. ; Almaini, A.E.A. ; Miller, J.F. ; McKenzie, L.
Author_Institution
Dept. of Electr. Electron. & Comput. Eng., Napier Univ., Edinburgh, UK
Volume
140
Issue
2
fYear
1993
fDate
3/1/1993 12:00:00 AM
Firstpage
105
Lastpage
108
Abstract
Describes Reed-Muller universal logic modules (RM-ULMs) and their use for the implementation of logic functions given in Reed-Muller (RM) form. A programmed algorithm is presented for the synthesis and optimisation of RM-ULM networks. The level-by-level minimisation procedure is based on the selection of control variables at different levels with the aim of maximising the number of discontinued branches and hence minimising the number of modules required to implement a given function. The algorithm is programmed in Fortran and can be used to realise fixed-polarity generalised Reed-Muller (GRM) expansions of any polarity and any number of variables.
Keywords
combinatorial circuits; logic CAD; RM-ULMs; Reed-Muller universal logic modules; level-by-level minimisation; logic functions; optimisation; synthesis;
fLanguage
English
Journal_Title
Computers and Digital Techniques, IEE Proceedings E
Publisher
iet
ISSN
0143-7062
Type
jour
Filename
210331
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