DocumentCode
885671
Title
Optimum Design of a Diode Squarer by Applying the Criterion of Square Root of the Integral of Per Cent Error Squared
Author
Deiters, Robert M.
Author_Institution
Department of Electrical Engineering, Sophia University, Tokyo, Japan.
Issue
3
fYear
1965
fDate
6/1/1965 12:00:00 AM
Firstpage
456
Lastpage
463
Abstract
Quarter-square diode analog multipliers are composed of two diode squaring channels. The selection of the diode breakpoints and the output level at each of them involves essentially the optimization of a straight-line segment approximation to the ideal parabolic output. This optimization has often been discussed and actually carried out in commercial multipliers using the least value of the integral of squared error as the optimization criterion. This and other published criteria, however, focus on smoothing the error, but allow a large per cent error in the region of small input. To smooth the per cent error over the whole range a new criterion of the square root of the integral of per cent error squared was applied. The design was carried out on a computer using a type of dynamic programming search process which allowed easy experimentation with the criterion as well as the easy incorporation of practical design requirements. The resulting design showed a substantially smoother per cent error over the entire range with only a very slight increase in per cent error in the region of higher inputs.
Keywords
Analog computers; Bandwidth; Circuits; Computer errors; Frequency; Light emitting diodes; Pulse modulation; Refining; Smoothing methods; Voltage;
fLanguage
English
Journal_Title
Electronic Computers, IEEE Transactions on
Publisher
ieee
ISSN
0367-7508
Type
jour
DOI
10.1109/PGEC.1965.264153
Filename
4038465
Link To Document