Manufacturable Parasitic-Aware Circuit-Level FETs in 65-nm SOI CMOS Technology

Author

Kim, Daeik ; Kim, Jonghae ; Plouchart, Jean-Olivier ; Cho, Choongyeun ; Trzcinski, Robert ; Lee, Sungjae ; Kumar, Mahender ; Norris, Christine ; Rieh, Jae-Sung ; Freeman, Greg ; Ahlgren, David

Author_Institution

IBM Semicond. Res. & Dev. Center, Hopewell Junction

Volume

28

Issue

6

fYear

2007

fDate

6/1/2007 12:00:00 AM

Firstpage

520

Lastpage

522

Abstract

This letter reports the statistical analysis of circuit-level FET high-speed performance in 65-nm silicon-on-insulator CMOS technology. Practical performance metrics are derived from full 300-mm wafer measurements. The proposed circuit-level layout wiring parasitics-aware FET reflects realistic FET that is placed in circuits. Its measurement and model are directly applicable to circuit design in conjunction with multiple layers of yield and manufacturability considerations. A stretched gate-pitch NFET design shows an average current gain cutoff frequency f_T of 250 GHz, with 7.6% standard deviation, 6.7% mismatch standard deviation, and maximum f_T of 307 GHz. The proposed characterization methodology will become more relevant to technologies beyond 65 nm.

Keywords

CMOS integrated circuits; field effect transistors; silicon-on-insulator; SOI CMOS technology; circuit design; circuit-level layout wiring parasitics-aware FET; gain cutoff frequency; manufacturability considerations; manufacturable parasitic-aware circuit-level FETs; silicon-on-insulator CMOS; size 65 nm; statistical analysis; stretched gate-pitch NFET design; wafer measurements; CMOS technology; Circuit synthesis; Cutoff frequency; FETs; Measurement; Semiconductor device modeling; Silicon on insulator technology; Statistical analysis; Virtual manufacturing; Wiring; 65-nm silicon-on-insulator (SOI) CMOS; Circuit-level FET with wiring parasitics; FET yield and manufacturability; current gain cutoff frequency $f_{T}$; full 300-mm wafer statistical analysis;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2007.897448

Filename

4212175