Title :
Cell-plate line connecting complementary bit-line (C3) architecture for battery-operated DRAMs
Author :
Asakura, Mikio ; Arimoto, Kazutami ; Hidaka, Hideto ; Fujishima, Kazuyasu
Author_Institution :
Mitsubishi Electr. Corp., Hyogo, Japan
fDate :
4/1/1992 12:00:00 AM
Abstract :
In low-voltage operating DRAMs, one of the most serious problems is how to maintain sufficient charge stored in the memory cell, which is concerned with the operating margin and soft error immunity. An array architecture called the cell-plate line connecting complementary bit-line (C3) architecture, which realizes a large signal voltage on the bit-line pair and low soft error rate (SER) without degrading the reliability of the memory cell capacitor dielectric film, is proposed. This architecture requires no unique process technology and no additional chip area. With the test device using the 16-Mb DRAM process, a 130-mV signal voltage is observed at 1.5-V power supply with 1.6-μm×3.2-μm cell size. This architecture should open the path for the future battery-backup and/or battery-operated high-density DRAMs
Keywords :
DRAM chips; MOS integrated circuits; memory architecture; 1.5 V; 16 Mbit; LV dynamic RAM; MOS IC; array architecture; battery-backup; capacitor dielectric film; cell-plate line connecting; complementary bit-line; low soft error rate; low-voltage operating DRAMs; memory cell; operating margin; soft error immunity; Capacitors; Degradation; Dielectric films; Error analysis; Joining processes; Power supplies; Random access memory; Signal processing; Testing; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
