DocumentCode :
886613
Title :
1 /spl mu/m MOSFET VLSI technology. III. Logic circuit design methodology and applications
Author :
Cook, Peter W. ; Schuster, Stanley E. ; Parrish, James T. ; Dilonardo, Victor ; Freedman, Darryl R.
Volume :
14
Issue :
2
fYear :
1979
fDate :
4/1/1979 12:00:00 AM
Firstpage :
255
Lastpage :
268
Abstract :
For pt. II see ibid., vol.SC14, no.2, p.247 (1979). Logic circuits were designed and fabricated in a 1 /spl mu/m silicon-gate MOSFET technology. First, conventional random logic chip images using the largely one-dimensional `Weinberger´ layout are examined. The image is able to provide chips with an average circuit delay of 3 ns at the 8000 circuit level of integration. Second, two forms of PLA and PLA-based macros are discussed. A dynamic PLA, used in a microprocessor cross section and including 105 product terms, which achieves a 56 ns cycle time is described. A static PLA, designed for 21-ns delay and achieving measured delays from 13 to 21 ns, is also described. Extensions, particularly into low-temperature operation, are discussed.
Keywords :
Cellular arrays; Field effect integrated circuits; Integrated circuit technology; Integrated logic circuits; Large scale integration; Logic design; cellular arrays; field effect integrated circuits; integrated circuit technology; integrated logic circuits; large scale integration; logic design; Delay; Design methodology; Image analysis; Integrated circuit measurements; Logic circuits; MOSFET circuits; Microprocessors; Programmable logic arrays; Very large scale integration; Wiring;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.1979.1051172
Filename :
1051172
Link To Document :
بازگشت