1 /spl mu/m MOSFET VLSI technology. VI. Electron-beam lithography

For pt.V see ibid., vol.SC14, no.2, p.275 (1979). The authors discuss the fabrication of 1 /spl mu/m minimum linewidth FET polysilicon-gate devices and circuits, with emphasis on vector-scan electron-beam technology and processing. Different types of 1 /spl mu/m MOSFET chips were written on 57 mm Si wafers using a totally automated electron-beam system. The pattern data were prepared by batch processing which includes proximity correction as well as sorting of shapes to achieve data compaction and minimal distance between shapes. A novel two-layer positive resist system has been developed to achieve reproducible liftoff profiles over topography and better linewidth control. The final results presented here demonstrate that there are no fundamental barriers to the extension of this work to small dimensions.