High-speed sensing techniques for ultrahigh-speed SRAMs

Author

Nambu, Hiroaki ; Kanetani, Kazuo ; Idei, Youji ; Homma, Noriyuki ; Yamaguchi, Kunihiko ; Hiramoto, Toshirou ; Tamba, Nobuo ; Odaka, Masanori ; Watanabe, Kunihiko ; Ikeda, Takahide ; Ohhata, Kenichi ; Sakurai, Yoshiaki

Author_Institution

Hitachi Ltd., Tokyo, Japan

Volume

27

Issue

4

fYear

1992

fDate

4/1/1992 12:00:00 AM

Firstpage

632

Lastpage

640

Abstract

Two high-speed sensing techniques suitable for ultrahigh-speed SRAMs are proposed. These techniques can reduce a 64-kb SRAM access time to 71~89% of that of conventional high-speed bipolar SRAMs. The techniques use a small CMOS memory cell instead of the bipolar memory cell that has often been used in conventional bipolar SRAMs for cache and control memories of mainframe computers. Therefore, the memory cell size can also be reduced to 26~43% of that of conventional cells. A 64-kb SRAM fabricated with one of the sensing techniques using 0.5-μm BiCMOS technology achieved a 1.5-ns access time with a 78-μm² memory cell size. The techniques are especially useful in the development of both ultrahigh-speed and high-density SRAMs, which have been used as cache and control memories of mainframe computers

Keywords

BIMOS integrated circuits; SRAM chips; 0.5 micron; 1.5 ns; 64 kbit; BiCMOS technology; CMOS memory cell; SRAM access time; high-density; high-speed sensing techniques; static RAM; ultrahigh-speed SRAMs; BiCMOS integrated circuits; CMOS memory circuits; CMOS technology; Circuit simulation; Delay effects; Laboratories; Random access memory; Velocity measurement; Very large scale integration; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.126554

Filename

126554