Title :
Empirical Modeling of Single-Event Upset (SEU) in NMOS Depletion-Mode-Load Static RAM (SRAM) Chips
Author :
Zoutendyk, J.A. ; Smith, L.S. ; Soli, G.A. ; Smith, S.L. ; Atwood, G.E. ; Thieberger, P.
Author_Institution :
Jet Propulsion Laboratory Cailfornia Institute of Technology Pasadena, California 91109
Abstract :
A detailed experimental investigation of single-event upset (SEU) in static RAM (SRAM) chips fabricated using a family of high-performance NMOS (HMOS) depletion-mode-load process technologies, has been done. Empirical SEU models have been developed with the aid of heavy-ion data obtained with a three-stage tandem van de Graaff accelerator. The results of this work demonstrate a method by which SEU may be empirically modeled in NMOS integrated circuits.
Keywords :
Integrated circuit modeling; Integrated circuit technology; Ion accelerators; Laboratories; MOS devices; Process design; Random access memory; Read-write memory; Single event upset; Variable structure systems;
Journal_Title :
Nuclear Science, IEEE Transactions on
DOI :
10.1109/TNS.1986.4334645
