Title :
Modeling of the diode input I/sup 2/L structure
Author :
Perlegos, Gust ; Chan, Shu-Park
fDate :
6/1/1979 12:00:00 AM
Abstract :
A high-speed single-collector multiinput Schottky diode I/SUP 2/L structure is presented. The structure features negligible p-n-p and a relatively low extrinsic base minority carrier storage, and lends to the near elimination of saturation. A theoretical model predicts that the structure produces circuit delays of better than 3 ns at 50 /spl mu/A.
Keywords :
Bipolar integrated circuits; Integrated logic circuits; Schottky-barrier diodes; Semiconductor device models; bipolar integrated circuits; integrated logic circuits; semiconductor device models; Circuits; Current density; Differential equations; Electrons; Impurities; Logic; Microprocessors; Propagation delay; Schottky diodes; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1979.1051230
