DocumentCode :
887792
Title :
The impact of multiple failure modes on estimating product field reliability
Author :
Carulli, John M., Jr. ; Anderson, Thomas J.
Author_Institution :
Silicon Technol. Dev. Div., Texas Instrum. Inc., TX, USA
Volume :
23
Issue :
2
fYear :
2006
Firstpage :
118
Lastpage :
126
Abstract :
A difficulty in reliability modeling is how to capture the impact of all of the various reliability defect types. The general approach to optimizing burn-in that we describe in this article addresses a multiple-defect environment. The approach has four main parts: (i) modeling the product´s failure rate distribution, (ii) establishing the Pareto distribution of reliability defects, (iii) assessing the kinetic information of each reliability defect, and (iv) estimating the DPPM under product use conditions. This article compares and contrasts the acceleration effects of various extrinsic defects found in 130- and 90-nm CMOS technology products.
Keywords :
CMOS integrated circuits; Pareto distribution; estimation theory; failure analysis; integrated circuit reliability; integrated circuit testing; CMOS technology products; DPPM estimation; multiple failure modes; product failure rate distribution; product field reliability estimation; reliability defect Pareto distribution; reliability defect kinetic information; IEEE Press; Integrated circuit reliability; Kinetic theory; Physics; Predictive models; Production; Semiconductor device modeling; Stress; Testing; Yield estimation; DPPM; burn-in; early failure rate; reliability;
fLanguage :
English
Journal_Title :
Design & Test of Computers, IEEE
Publisher :
ieee
ISSN :
0740-7475
Type :
jour
DOI :
10.1109/MDT.2006.53
Filename :
1613792
Link To Document :
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