• DocumentCode
    888240
  • Title

    Fully Integrated AC Coupled Interconnect Using Buried Bumps

  • Author

    Wilson, John ; Mick, Stephen ; Xu, Jian ; Luo, Lei ; Bonafede, Salvatore ; Huffman, Alan ; LaBennett, Richard ; Franzon, Paul D.

  • Author_Institution
    North Carolina State Univ., Raleigh
  • Volume
    30
  • Issue
    2
  • fYear
    2007
  • fDate
    5/1/2007 12:00:00 AM
  • Firstpage
    191
  • Lastpage
    199
  • Abstract
    Presented is the complete demonstration of an assembled system using AC coupled interconnect (ACCI) and buried solder bumps. In this system, noncontacting input/output (I/O) are created by using half-capacitor plates on both a chip and a substrate, while buried solder bumps are used to provide power/ground distribution and physical alignment of the coupling plates. ACCI using buried bumps is a technology that provides a manufacturable solution for noncontacting I/O signaling by integrating high-density, low inductance power/ground distribution with high-density, high-speed I/O. The demonstration system shows two channels operating simultaneously at 2.5 Gb/s/channel with a bit error rate less than 10-12, across 5.6 cm of transmission line on a multichip module (MCM). Simple transceiver circuits were designed and fabricated in a 0.35 -mum complementary metal-oxide-semiconductor (CMOS) technology, and for PRBS-127 data at 2.5 Gb/s transmit and receive circuits consumed 10.3 mW and 15.0 mW, respectively. This work illustrates the increasing importance of chip and package co-design for high-performance systems.
  • Keywords
    CMOS integrated circuits; error statistics; integrated circuit design; integrated circuit interconnections; integrated circuit packaging; multichip modules; solders; transceivers; bit error rate; bit rate 2.5 Gbit/s; buried solder bumps; chip package co-design; complementary metal-oxide-semiconductor technology; half-capacitor plates; integrated AC coupled interconnects; multichip module; noncontacting I/O signaling; noncontacting input-output; power 10.3 mW; power 15.0 mW; power-ground distribution; size 0.35 mum; size 5.6 cm; transceiver circuits design; transmission line; Assembly systems; Bit error rate; CMOS technology; Distributed parameter circuits; Inductance; Integrated circuit interconnections; Manufacturing; Multichip modules; Power system interconnection; Power transmission lines; AC coupled interconnect (ACCI); MCM; buried bumps; capacitive coupling; chip and package co-design; noncontacting I/O; pulse signaling;
  • fLanguage
    English
  • Journal_Title
    Advanced Packaging, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1521-3323
  • Type

    jour

  • DOI
    10.1109/TADVP.2007.896920
  • Filename
    4214920