A comprehensive approach for the analysis of package induced stress in ICs using analytical and empirical methods

Integrated circuit device failures induced by package stress are classifiable into two broad categories: those involving device parametric shifts resulting from the piezoresistive properties of silicon; and those involving permanent damage to interconnect features such as metal, dielectric, and passivation layer. The relevance of one or both of these failure modes to different device types is considered. The design and use of suitable test chips to address such failure modes is discussed. The application of the finite element modeling (FEM) technique to analyze package stress is demonstrated. An approach involving the combination of FEM with empirical test chip data to considerably enhance the predictive capability of FEM is presented