Leakage-current reduction in thin Ta₂O₅ films for high-density VLSI memories

Author

Hashimoto, Chisato ; Oikawa, Hideo ; Honma, Nakahachiro

Author_Institution

Electr. Commun. Lab., NTT, Atsugi, Japan

Volume

36

Issue

1

fYear

1989

fDate

1/1/1989 12:00:00 AM

Firstpage

14

Lastpage

18

Abstract

Key techniques for applying Ta₂O₅ film to megabit-class MOS DRAMs are presented. A high-purity (4N and up) Ta sputtering target is developed to obtain high-purity Ta₂O₅ film. The leakage current in Ta₂O₅ film that is deposited using a clean sputtering system with this high-purity target is far lower than that of film deposited with a conventional target. A previous drawback of Ta₂O₅, the decrease of effective dielectric constant as thickness decreases, is solved by using Mo as an electrode material. The leakage current increase that results from using metal as a bottom electrode is suppressed by reducing the electrode asperity. MOS DRAMs of up to 16-Mb capacity can be attained without trench technology by using these techniques

Keywords

MOS integrated circuits; VLSI; dielectric thin films; integrated memory circuits; leakage currents; permittivity; random-access storage; sputtered coatings; tantalum compounds; 16 Mbit; MOS DRAMs; Mo; effective dielectric constant; electrode asperity; high-density VLSI memories; leakage current; sputtering target; thin Ta₂O₅ films; Dielectric constant; Dielectric materials; Electrodes; Laboratories; Leakage current; MOS capacitors; Purification; Semiconductor impurities; Sputtering; Very large scale integration;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.21171

Filename

21171

Leakage-current reduction in thin Ta2O5 films for high-density VLSI memories

Hashimoto, Chisato ; Oikawa, Hideo ; Honma, Nakahachiro

jour

Leakage-current reduction in thin Ta₂O₅ films for high-density VLSI memories