Integrated complementary MOS circuit

Regions of p and n silicon were obtained on the same substrate using a modified etch and refill technique. n- and p-channel enhancement mode MOS transistors were fabricated in these regions. The depletion of boron from the silicon surface was minimized by the use of low-temperature pyrolytic oxide for the diffusion mask and the insulator of the MOS transistors. An integrated complementary MOS memory circuit constructed with the aforementioned techniques exhibited a standby power dissipation of 8.4 µW at 12 volts supply.