Single-chip per channel codec with filters utilizing Δ-Σ modulation

A single-chip per channel codec with filters, fabricated using a single poly-Si NMOS technology, is discussed. In the encoder, the analog signal is converted to a 2.048 M samples/s digital signal by a Δ-Σ modulator. Filtering necessary for the sampling rate 8 k sample/s and compression by the μ255 law are performed digitally. In the decoder, the 8 k samples/s PCM is successively resampled and converted into the 2.048 M samples/s Δ-Σ signal, which is then decoded by a Δ-Σ demodulator. All the high-frequency images, which appear around multiples of 8 kHz, are removed by digital filters. The chip has continuous-signal antialiasing and smoothing filters for the 2.048 Samples/s sampling rate. It also has reference voltage generators for Δ-Σ modulation/demodulation. Some of the observed characteristics are given. The NMOS Δ-Σ modulator requires only two on-chip matched capacitors as precision components, and does not require a linear amplifier. A deliberate quantization step imbalance is introduced to allow a low sampling rate. The main band limiting for the 8 k samples/s is done by the recursive filter. This is realized with the serial-parallel pipeline multiplier (SPPM) in four-phase logic. The whole system is integrated on a 296 mil×342 mil chip.