DocumentCode
891000
Title
A CMOS pipelined single channel digital echo canceller
Author
Mitchler, D.W. ; Elmasry, M.I.
Volume
16
Issue
4
fYear
1981
Firstpage
377
Lastpage
379
Abstract
Recent advances in LSI/VLSI have made the integration of digital echo cancellers both feasible and economical. The design presented features a universal CMOS ALU which is capable of direct I/O with /spl mu/-law encoded data. The ALU is pipelined to achieve high processing speed with low power dissipation. Based on this /spl mu/-law ALU, a 128-tap CMOS pipelined single channel digital echo canceller was designed and simulated, and a prototype was built. Experimental results for a 4 kHz sampling rate are presented.
Keywords
Digital integrated circuits; Echo suppression; Field effect integrated circuits; Large scale integration; digital integrated circuits; echo suppression; field effect integrated circuits; large scale integration; Computational modeling; Computer simulation; Delay; Echo cancellers; Hardware; Large scale integration; Power dissipation; Sampling methods; Speech; Virtual prototyping;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1981.1051604
Filename
1051604
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