High-speed split-emitter I/sup 2/L/MTL memory cell

Describes a novel circuit/device approach that overcomes the performance drawback of the injection-sensed I/SUP 2/L/MTL memory cell cited in a 16-kbit static MTL RAM (see IEEE ISSCC Dig. Tech. Papers, p.222-4, 1980). As a result, a compact memory cell with extremely low DC standby power in the nanowatt range and with read/write times below 5 ns is achieved. This has been verified by experimental investigations on small test arrays. They have been fabricated with an advanced process featuring a p-polysilicon-base self-alignment scheme and a double-diffused p-n-p structure. In addition, computer circuit simulations have been performed that show the read delay sensitivities in large arrays. Based on these results, an access time of less than 25 ns is projected for a 16-kbit MTL RAM.