DocumentCode
891199
Title
A 16 DIP, 64 kbit, static MOS-RAM
Author
Wada, Toshio ; Yamanaka, Hiroshi ; Sakamoto, Mitsuru ; Yamamoto, Hirohiko ; Matsue, Shigeki
Volume
16
Issue
5
fYear
1981
Firstpage
488
Lastpage
491
Abstract
A 64K/spl times/1 bit fully static MOS-RAM has been fabricated. For the purpose of replacement of 64 kbit dynamic RAM, this static RAM has been designed to be assembled in a standard 300 mil 16 pin DIP. It is the first time address multiplexing has been in static RAMs. The device with multiple addressing and improved row decoder employs a double poly Si layer and a 1.5 /spl mu/m design rule which is achieved by advanced process technology. As a result, the RAM has a 11.0 /spl mu/m/spl times/26.5 /spl mu/m (291.5 /spl mu/m/SUP 2/) cell size and a 3.84 mm/spl times/7.40 mm (28.40 mm/SUP 2/) chip size. The address access time is less than 150 ns with an active power dissipation of 400 mW.
Keywords
Field effect integrated circuits; Integrated memory circuits; Large scale integration; Random-access storage; field effect integrated circuits; integrated memory circuits; large scale integration; random-access storage; Assembly; Circuits; DRAM chips; Dry etching; Electronics packaging; Ion implantation; Random access memory; Read-write memory; Resistors; Space technology;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1981.1051627
Filename
1051627
Link To Document