An electrically alterable PLA for fast turnaround-time VLSI development hardware

An electrically alterable PLA (EAPLA) has been designed in double polysilicon FET technology to serve as fast turnaround-time development hardware for custom VLSI designs. Included are descriptions of the cell design, the unique circuitry that is used, the chip architecture and a description of the PLA-based design system incorporating the EAPLA. The PLA architecture consists of two arrays cascaded to perform AND-OR combinational logic functions. It has 24 inputs (2-bit partitioning), 76 product terms, and 28 outputs. Sixteen of the product terms and all of the outputs are `dottable´ off-chip with modules of the same type to meet larger PLA requirements. Four modules can be dotted at each array output.