A digital signal processing architecture for iterative deconvolution restoration algorithms

Author

Whitted, Rodney B. ; Crilly, Paul Benjamin

Author_Institution

Dept. of Electr. & Comput. Eng., Tennessee Univ., Knoxville, TN, USA

Volume

41

Issue

1

fYear

1992

fDate

2/1/1992 12:00:00 AM

Firstpage

147

Lastpage

151

Abstract

A VLSI DSP chip that will significantly improve the processing throughput for a general class of iterative deconvolution algorithms is presented. The design is based on a systolic array concept. This will enable these algorithms to be used for real-time DSP applications which formerly, due to speed limitations, were not possible. The increased class of applications will enable further understanding of these applications. The higher throughput will also enable the researcher to further take advantage of the features unique to iterative deconvolution

Keywords

VLSI; computer architecture; digital signal processing chips; iterative methods; systolic arrays; VLSI DSP chip; convolution array; digital signal processing architecture; interfaces; iterative deconvolution restoration algorithms; real-time DSP; systolic array; Additive noise; Deconvolution; Digital signal processing; Digital signal processing chips; Iterative algorithms; Signal processing algorithms; Signal restoration; Spectroscopy; Throughput; Wiener filter;

fLanguage

English

Journal_Title

Instrumentation and Measurement, IEEE Transactions on

Publisher

ieee

ISSN

0018-9456

Type

jour

DOI

10.1109/19.126650

Filename

126650