Experimental analysis and new modeling of MOS LSI yield associated with the number of elements

A new modeling and an analysis of the fabricated MOS LSI yield are presented. LSI processing defects generated in fabrication steps have been classified using monitors introduced simultaneously into the same fabrication steps as for the LSIs. The MOS LSI yield Y is given by Y=exp (-(D/SUB LO/+Σ/SUB i/m/SUB i/×D/SUB Lai/)), where D/SUB LO/ is the logarithmic probability for cluster occurrence, m/SUB i/ is the number of elements in the ith kind of critical structure group, and D/SUB Lai/ is the average logarithmic failure probability per element for the ith kind of critical structure group. Pinholes in the gate oxide, underetching in contact hole etching through the second intermediate insulator layer, and clustered pinholes in the first intermediate insulator layer play important roles in regard to the present fabricated LSI yield. Pinholes in the gate oxide are the most important factor for evaluation of MOS LSI yield, and failure probability of the gate oxide is mainly related to perimeter length.