DocumentCode :
892947
Title :
A redundancy circuit for a fault-tolerant 256K MOS RAM
Author :
Mano, Tsuneo ; Wada, Masato ; Ieda, Nobuaki ; Tanimoto, Masafumi
Volume :
17
Issue :
4
fYear :
1982
Firstpage :
726
Lastpage :
731
Abstract :
A multiple word/bit line redundancy technique introduced into a fault-tolerant 256K MOS RAM is described. The address of the defective lines are stored in spare decoders and defective lines are replaced by redundant lines. New electrically programmable elements are used in these spare decoders. Yield improvement as a result of the implementation of the redundant lines is discussed, and a detailed description of the redundancy circuit design is given. The redundancy occupies less than 10 percent of the whole chip area of the 256K MOS RAM. The good (defect-free) chip functions without any degradation of speed and power caused by the redundancy, while the power consumption and access time increases in the repaired chip are 10 and 25 percent, respectively.
Keywords :
Fault tolerant computing; Field effect integrated circuits; Integrated memory circuits; Random-access storage; Redundancy; fault tolerant computing; field effect integrated circuits; integrated memory circuits; random-access storage; redundancy; Circuit synthesis; Decoding; Degradation; Energy consumption; Fault tolerance; Laser beams; MOSFET circuits; Optical device fabrication; Read-write memory; Redundancy;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.1982.1051803
Filename :
1051803
Link To Document :
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