Flip-flop resolving time test circuit

Integrated circuit flip-flop resolving time parameters, required for calculation of synchronizer performance and reliability, are measured by wafer probing, without the need for dicing or bonding, by incorporation of test structures on an IC along with the flip-flop to be measured. The circuit has five digital inputs, five digital outputs, including one for frequency measurements, and two analog inputs plus power and ground connections. Several delays that are fabricated as part of the test circuit, including a voltage controlled delay with a few picosecond resolution, are calibrated as part of the test procedure by grating them into and out of the delay path of a ring oscillator. Each of the delay values is calculated by subtracting the period of the ring oscillator with the delay omitted, from the period of the ring oscillator with the delay included. A frequency divider is fabricated as part of the test structure to reduce the output of the ring oscillator to less than 200 kHz so no high-frequency inputs of outputs from the IC are required.