A low power resistive load 64 kbit CMOS RAM

A fully asynchronous 8K word/spl times/8 bit CMOS static RAM with high resistive load cells is described. For fabricating the RAM, an advanced double polysilicon 2 /spl mu/m CMOS technology has been developed. Internally clocked dynamic peripheral circuits with address transition detectors are implemented to achieve high speed and low power simultaneously. A new CMOS fault-tolerant circuit technology is also introduced for improving fabrication yield without sacrificing operating speed or standby power. The resulting cell size and die size are 15/spl times/19 /spl mu/m and 4.87/spl times/7.22 mm, respectively. The RAM offers, typically, 70 ns access time, 15 mW operating power, and 10 /spl mu/W standby power.