10 ns 8x8 multiplier LSI using super self-aligned process technology

Author

Yamauchi, Hironori ; Nikaido, Tadanobu ; Nakashima, Takayoshi ; Kobayashi, Yoshiji ; Sakai, Tetsushi

Volume

18

Issue

2

fYear

1983

fDate

4/1/1983 12:00:00 AM

Firstpage

204

Lastpage

210

Abstract

Describes a high-speed 8/spl times/8 bit multiplier LSI which uses the newly developed high-speed and low-power bipolar process technology SST-2. SST-2 results in 250 ps delay time and 0.165 pJ power delay product in a low-level current mode logic (LCML) gate. Its multiplication time is about 10 ns, and its power dissipation is about 660 mW. This LSI has a feature called `perfect expandability´ for arbitrary scaling of the expanded 8n/spl times/8n bit multiplier without an additional circuit. The results indicate that 32/spl times/32 bit multiplication can be carried out with 55 ns.

Keywords

Bipolar integrated circuits; Digital arithmetic; Integrated circuit technology; Integrated logic circuits; Large scale integration; bipolar integrated circuits; digital arithmetic; integrated circuit technology; integrated logic circuits; large scale integration; Adders; Algorithm design and analysis; Application software; Circuits; Delay effects; Digital signal processing; Large scale integration; Logic gates; Paper technology; Signal processing algorithms;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1983.1051923

Filename

1051923