DocumentCode
894115
Title
Comments on "Silicon MESFET digital circuit techniques"
Author
Houston, T.W. ; Darley, H.M.
Volume
18
Issue
2
fYear
1983
fDate
4/1/1983 12:00:00 AM
Firstpage
229
Lastpage
230
Abstract
See also ibid., vol.SC-16, p.578-84 (Oct. 1981). It is shown that the design criterion for MESFET ED logic assumed by Hartgring et al.-that the low voltage level must be less than /SUP 1///SUB 3/ V/SUB T/-is overly restrictive, and that the technology is more tolerant of V/SUB T/ variation than would be surmised from such an assumption. Data for the operation of a MESFET ED logic divide-by-four circuit over a temperature range from 25/spl deg/C to 145/spl deg/C confirms the wider operating margin of this technology.
Keywords
Integrated logic circuits; Schottky gate field effect transistors; integrated logic circuits; CMOS process; Capacitors; Digital circuits; Distortion; Driver circuits; Equivalent circuits; MESFET circuits; Operational amplifiers; Power supplies; Silicon;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1983.1051929
Filename
1051929
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