Title :
A 256 kbit ROM with serial ROM cell structure
Author :
Cuppens, Roger ; Sevat, L.H.M.
fDate :
6/1/1983 12:00:00 AM
Abstract :
The realization of a 256 kbit ROM using a 500 /spl Aring/ E/D NMOS technology is described. A high packaging density has been achieved by using a NAND structure in the memory array and in the decoders. Some characteristics of this serial ROM structure are discussed and compared with the conventional parallel configurations. The 32K/spl times/8 bit ROM with a bit size of 5.25/spl times/5.5 /spl mu/m/SUP 2/ has a total chip area of 18.6 mm/SUP 2/. Operating from a single 5 V supply, the device has a typical access time of 850 ns with a minimum cycle time of 1500 ns and dissipates 70 mW. In the power-down mode this power is reduced to 5 mW.
Keywords :
Cellular arrays; Field effect integrated circuits; Integrated memory circuits; Read-only storage; cellular arrays; field effect integrated circuits; integrated memory circuits; read-only storage; Bipolar transistors; Broadband amplifiers; Electronic circuits; Optical amplifiers; Read only memory; Solid state circuits; Speech synthesis; Synthesizers; Telecommunications; Telephony;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1983.1051949
