A low-power sub 100 ns 256K bit dynamic RAM

Author

Fuji, S. ; Natori, Kenji ; Furuyama, Tohru ; Saito, Shozo ; Toda, Haruki ; Tanaka, Takeshi ; Ozawa, Osamu

Volume

18

Issue

5

fYear

1983

Firstpage

441

Lastpage

446

Abstract

A 256K-word /spl times/ 1-bit NMOS dynamic RAM using 2-/spl mu/m design rules and MoSi/SUB 2/ gate technology is described. A marked low-power dissipation of 170 mW (5 V V/SUB cc/, 260-ns cycle time) has been achieved by using a partial activation scheme. Optimized circuits exhibit a typical CAS access time of 34 ns. For the purpose of optimizing circuit parameters, an electron beam tester was successfully applied to observe the internal timing of real chips. Laser repairable redundancy with four spare rows and four spare columns is implemented for yield improvement.

Keywords

Field effect integrated circuits; Integrated circuit technology; Integrated memory circuits; Large scale integration; Laser beam applications; Random-access storage; Redundancy; field effect integrated circuits; integrated circuit technology; integrated memory circuits; large scale integration; laser beam applications; random-access storage; redundancy; Capacitance; Capacitors; Circuit testing; DRAM chips; Electron beams; Power dissipation; Random access memory; Read-write memory; Silicides; Timing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1983.1051975

Filename

1051975