DocumentCode :
894559
Title :
A sub-100 ns 256K DRAM with open bit line scheme
Author :
Nakano, Tomio ; Yabu, Takashi ; Noguchi, Eiji ; Shirai, Kazunari ; Miyasaka, Kiyoshi
Volume :
18
Issue :
5
fYear :
1983
Firstpage :
452
Lastpage :
456
Abstract :
A 256K DRAM with a 34.1 mm/SUP 2/ die size and a typical access time of 70 ns has been fabricated by using a newly designed boosted high-level clock generator circuit and triple poly-Si processing. For two-cell array configurations and sensing schemes, the available signal and uncommon mode noise levels at the input terminal of the sense amplifiers were studied. It was concluded that the open bit line configuration was the better one for a high-speed 256 kbit DRAM with a small die size, and the device characteristics obtained confirmed this approach. The device can operate in the nibble mode with a 15-ns access time from a CAS clock and can be refreshed with CAS before RAS automatic refresh mode. The yield has been enhanced with optimized redundancy.
Keywords :
Field effect integrated circuits; Integrated circuit technology; Integrated memory circuits; Large scale integration; Random-access storage; field effect integrated circuits; integrated circuit technology; integrated memory circuits; large scale integration; random-access storage; Circuit noise; Clocks; Content addressable storage; Electric variables; Noise level; Random access memory; Redundancy; Semiconductor device noise; Voltage;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.1983.1051977
Filename :
1051977
Link To Document :
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