A 256K dynamic RAM with page-nibble mode

Author

Fujishima, Kazuyasu ; Ozaki, Hideyuki ; Miyatake, Hideshi ; Uoya, Shigeo ; Nagatomo, Masao ; Saitoh, Kazunori ; Shimotori, Kazuhiro ; Oka, Hisao

Volume

18

Issue

5

fYear

1983

Firstpage

470

Lastpage

478

Abstract

A 5-V 256K /spl times/ 1 bit NMOS dynamic RAM with page-nibble mode is designed and fabricated using 2-/spl mu/m design rules and folded bit-line configuration. Molybdenum disilicided polysilicon is used as the second-level gate to reduce the word-line signal delay. A large 98 /spl mu/m/SUP 2/ cell with Hi-C structure stores the signal charge of 210 fC and provides this memory with wide operating margin. The device is immune to voltage bumping and uses laser programmable redundancy. Typical RAS/CAS access times are 80 ns/40 ns. An average operating current of 50 mA with 80 mA peak at 230 ns cycle time and standby current of 2 mA are achieved.

Keywords

Field effect integrated circuits; Integrated circuit technology; Integrated memory circuits; Large scale integration; Random-access storage; field effect integrated circuits; integrated circuit technology; integrated memory circuits; large scale integration; random-access storage; Circuits; Content addressable storage; DRAM chips; Decoding; Delay; MOS devices; Random access memory; Read-write memory; Redundancy; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1983.1051980

Filename

1051980