A 4.5 ns access time 1K x 4 bit ECL RAM

Author

Nokubo, Jyoji ; Tamura, Teiji ; Nakamae, Masahiko ; Shiraki, Hiroyuki ; Ikushima, Takayashu ; Akashi, Tsutomu ; Mayumi, Hiroshi ; Kubota, Takehiko ; Nakamura, Toshio

Volume

18

Issue

5

fYear

1983

Firstpage

515

Lastpage

520

Abstract

An extremely high-speed ECL 4-kbit RAM with maximum access time of 4.5 ns and typical power dissipation of 1.5 W has been developed for cache memories and control store. This performance has been realized by using a very shallow junction transistor with an emitter size of 1.3 /spl times/ 1.5 /spl mu/m, which has a high cutoff frequency of 9 GHz, in conjunction with optimized circuit design. The RAM was housed in a small leadless chip carrier (LCC) package. The overall package size was 0.335 in/SUP 2/. The RAM was designed to have soft-error immunity. The failure rate due to alpha particles has been estimated, through acceleration tests, to be less than 50 FIT.

Keywords

Bipolar integrated circuits; Emitter-coupled logic; Integrated circuit technology; Integrated memory circuits; Large scale integration; Random-access storage; bipolar integrated circuits; emitter-coupled logic; integrated circuit technology; integrated memory circuits; large scale integration; random-access storage; Alpha particles; Cache memory; Capacitance; Circuit synthesis; Cutoff frequency; Epitaxial layers; Error correction codes; Packaging; Read-write memory; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1983.1051986

Filename

1051986